1. Field of the Invention
The present invention relates generally to computer systems. More particularly, the present invention relates to circuitry that forms a communications "bridge" between components in a personal computer system. Still more particularly, the present invention relates to a bridge logic device that includes an internal modular target expansion bus for facilitating the transfer of data between an internal target and an external master device that operates according to a protocol different than the internal modular expansion bus.
2. Background of the Invention
A personal computer system includes a number of components with specialized functions that cooperatively interact to produce the many effects available in modern computer systems. The ability of these various components to exchange data and other signals is vital to the successful operation of a computer system. One of the critical requirements in designing a new computer system is that all system components (including those that may be added to the system by a user) must be compatible. A component is compatible if it effectively communicates and transfers data without interfering or contending with the operation of other system components. Because modem computer systems are designed with components that operate with different protocols, the likelihood that components may not properly communicate is heightened. Compatibility between devices with different protocols is achieved, at least in part, with bridge logic devices. As the name implies, bridge logic devices provide a communications "bridge" between components and busses operating according to different protocols. The present invention is directed to an improved bridge logic device.
Computer systems have components with different protocols because of the manner in which computers evolved, and the desire to make new computer designs backwards-compatible with prior designs. This backward compatibility insures that the user can use a peripheral device from a prior computer in a new computer system. Early computer systems had relatively few components. As an example, some of the early computer systems included a processor (or CPU), random access memory (RAM), and certain peripheral devices such as a floppy drive, a keyboard and a display. These components typically were coupled together using a network of address, data and control lines, commonly referred to as a "bus." As computer technology evolved, it became common to connect additional peripheral devices to the computer through ports (such as a parallel port or a serial port), or by including the peripheral device on the main system circuit board (or "motherboard") and connecting it to the system bus.
The computer operates by having data flow through the system, with modification of the data occurring frequently. Typically, the CPU controls most of the activities of the computer system. The CPU supervises data flow and is responsible for most of the high-level data modification in the computer. The CPU, therefore, is the "heart" of the system and receives signals from the peripheral devices, reads and writes data to memory, processes data, and generates signals controlling the peripheral devices.
Despite the importance of the processor, the performance of the computer system is determined only in part by the speed and efficiency of the processor. Other factors also affect system performance. One of the most critical factors is the bus that interconnects the various system components. The size and clock speed of the bus dictate the maximum amount of data that can be transmitted between components. One early bus that still is in use today is the ISA (Industry Standard Architecture) bus. The ISA bus, as the name implies, was a bus standard adopted by computer manufacturers to permit the manufacturers of peripheral devices to design devices that would be compatible with most computer systems. The ISA bus includes 16 data lines and 24 address lines and operates at a clock speed of 8 MHz. A large number of peripheral components have been developed over the years to operate with the ISA protocol.
Since the introduction of the ISA bus, computer technology has continued to evolve at a relatively rapid pace. New peripheral devices have been developed, and both processor speeds and the size of memory arrays have increased dramatically. In conjunction with these advances, designers have sought to increase the ability of the system bus to transfer more data at a faster speed. One way in which the system bus has been made more effective is to permit data to be exchanged in a computer system without the assistance of the CPU. To implement this design, however, a new bus protocol had to be developed. One such bus that permits peripheral devices to run master cycles independently of the CPU is the EISA (Extended Industry Standard Architecture) bus. The EISA bus enables various system components residing on the EISA bus to obtain mastership of the bus and to run cycles on the bus. Another bus that has become increasingly popular is the Peripheral Component Interconnect (PCI) bus. Like the EISA bus, the PCI bus has bus master capabilities. The PCI bus also operates at clock speeds of 33 MHz or faster. Current designs contemplate implementing a 100 MHz PCI bus.
Because of the bus mastering capabilities and other advantages of the PCI (and EISA) bus, many computer manufacturers now implement one or the other of these busses as the main system bus in the computer system. Because of the proliferation of devices that had been developed for the ISA bus, the computer manufacturers also continued to provide an ISA bus in the computer system to permit the use of the many peripheral devices that operated under that protocol. To further provide flexibility, some computer manufacturers provide all three busses in the same computer system to permit users to connect peripheral devices of all three protocols to the computer system. To implement these various busses in the same computer system, special bridge logic circuit has been developed to interface to the various busses.
FIG. 1 shows a representative prior art computer system that includes a CPU coupled to a bridge logic device via a CPU bus. The bridge logic device is sometimes referred to as a "North bridge" for no other reason than it often is depicted at the upper end of a computer system drawing. The North bridge also couples to the main memory array by a memory bus. The North bridge couples the CPU and memory to the peripheral devices in the system through a PCI bus or other expansion bus (such as an EISA bus). Various components that understand PCI protocol may reside on the PCI bus, such as a graphics controller.
If other secondary expansion busses are provided in the computer system, another bridge logic device typically is used to couple the PCI bus to that expansion bus. This bridge logic is sometimes referred to as a "South bridge" reflecting its location vis-a-vis the North bridge in a typical computer system drawing. An example of such bridge logic is described in U.S. Pat. No. 5,634,073, assigned to Compaq Computer Corporation. In FIG. 1, the South bridge couples the PCI bus to an ISA bus. Various ISA-compatible devices are shown coupled to the ISA bus.
As one skilled in the art will understand, devices residing on the ISA bus may be targets for devices coupled to the PCI bus, including the CPU. Thus, even though the CPU is not directly connected to the ISA bus, it may still need to read and write data, or perform other operations, to devices on that bus. The PCI protocol permits devices residing on the PCI to run master cycles to targets residing on the PCI bus. To permit devices on other busses to run master cycles on the PCI bus to the secondary expansion busses such as the ISA bus, an interface controller for secondary expansion busses and other peripheral devices coupled to the South bridge must be included in the South bridge logic. This interface controller converts the PCI signals to ISA signals for target cycles to the South bridge. Thus, the interface controller for the ISA bus must understand the protocol of both busses. As an example, if the designer wanted to permit the CPU or some other PCI peripheral to run master cycles on the PCI bus to the hard drive, then a hard drive interface controller would be provided in the South bridge logic that was capable of receiving signals from the PCI bus and translating the PCI signals to IDE signals. If the hard drive also could be a PCI master, the hard drive controller in the South bridge also had to be capable of driving PCI master cycles. Similarly, if the modem could also function as a PCI target and master, then an associated controller must also be provided in the South bridge logic to receive and process PCI signals from PCI masters, and also to assert master signals on the PCI bus.
One of the problems with previous South bridges is that the controllers translated signals from one protocol of an external bus to a non-standard protocol internal to the bridge that often varied from controller to controller. Such South bridges were then forced to include complicated, extensive logic to interface to each of the internal controllers. In addition, every time that another expansion bus peripheral was added, the PCI controller for the South bridge logic must be extensively re-designed to interface to the new peripheral. Similarly, every time that the expansion bus changes or is replaced with a different design, each interface controller must be re-designed to be made compatible with the new expansion bus protocol. To date, no one has developed a bridge logic device that overcomes these deficiencies.